General Configuration Register; Table 23-14. Gc Register; Table 23-15. Gc Register Definitions - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary
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Analog-to-Digital Converter/Brownout Detector

23.3.2.6 General Configuration Register

GC is the General Configuration Register. The active bits used in this register are
Read/Write.
In this register, the SSM signal triggers the state machine to retrieve the data from the con-
trol bank and store it in the appropriate registers for the ADC. If the SSM bit is set to 11 at
the end of a sequence, the state machine continues to convert data.
If the SSM bits are set to 10 and a value of 0b0000110 is written to the GC Register, the
EOSINTR_UM bit (bit [2]) of the Interrupt Status Register may never get set. This is normal
operation. To accommodate this, wait two A2DCLK periods after setting the SSM bit to 10
before setting the SSB bit.
NOTE: Allow two A2DCLK cycles between successive write cycles to this register. Otherwise, ADC behavior
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:7
6:3
FIFOWMK
2
1:0
23-16
can become erratic.
31
30
29
28
27
0
0
0
0
R
R
R
R
15
14
13
12
11
0
0
0
0
R
R
R
R

Table 23-15. GC Register Definitions

NAME
Reserved Read as zero.
///
FIFO Watermark Programmed to values between 0 and 15. This value cor-
responds to watermark levels between 1 and 16, respectively. When the FIFO
fills to this level, the FIFO generates an interrupt.
Start Sequence Bit
SSB
0 = SSB will not start conversion sequence.
1 = SSB will start conversion sequence.
Sequence Start Mode
00 = SSB or Pen Interrupt starts new conversions.
01 = Pen Interrupt starts new conversions.
10 = SSB starts new conversions.
11 = Continuous conversions.
SSM
To trigger continuous conversions, set these bits to '11', wait one A2DCLK
period, and set the SSB bit to '1'. Thereafter, once any conversions occur and
SSM is set to '00' to stop the conversions, conversions can be started again
by setting SSM to '11', without having to set SSB. Note that the Pen Interrupt
can only be used when the ADC is configured to start on Pen Down. For more
information, see Section 23.3.2.7.
LH75400/01/10/11 (Preliminary) User's Guide

Table 23-14. GC Register

26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
///
0
0
0
0
0
R
R
R
R
R
0xFFFC3000 + 0x14
DESCRIPTION
6/25/03
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
FIFOWMK
SSB
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
R
R
1
0
SSM
0
0
RW
RW

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