Raw Interrupt Status Register; Table 14-21. Status Register; Table 14-22. Status Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

14.3.2.9 Raw Interrupt Status Register

Status is the Raw Interrupt Status Register. This register is Read/Write.
• On a read, this register returns five bits that may generate interrupts when set.
• On writes to this register, a bit value of '1' clears the interrupt corresponding to that bit.
Writing a '0' has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:5
4
3
2
1
0

Table 14-21. Status Register

31 30 29 28 27
0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0
R R R R R

Table 14-22. Status Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Master Bus Error Interrupt Asserted when an ERROR response is re-
ceived by the master interface during a transaction with a slave. When such
MBERROR
an error is encountered, the master interface enters an error state and re-
mains in this state until clearance of the error has been signaled to it.
Vertical Compare Interrupt Asserted when one of four vertical display re-
gions, selected via the LCD Control Register with bits [13:12], is reached.
VCOMP
The interrupt can be made to occur at the start of Vertical Synchronization,
Back Porch, Active Video, and Front Porch.
LCD Next Base Address Update Interrupt Asserted when either the
UPBASE or the LPBASE values have been transferred to the UPCURR or
LNBU LPCURR incrementer, respectively. This indicates to the system that it can
safely update the UPBASE or the LPBASE Register with new frame base
addresses if required.
FIFO Underflow Interrupt Asserted when internal data is requested from
an empty LCD DMA FIFO. Internally, individual upper and lower panel LCD
FUF
DMA FIFO Underflow Interrupt signals are generated, and this is the single
combined version of these.
/// Reserved Writing to this bit has no effect. Reading returns 0.
26 25 24 23
///
0 0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0 0
R R R R
0xFFFF4000 + 0x20
DESCRIPTION
6/17/03
Liquid Crystal Display Controller
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
0 0 0 0 0
R R RC RC RC
17 16
0 0
R R
1 0
FUF ///
0 0
RC R
14-17