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Chapter 19
UART0 and UART1
UART0 and UART1 offer similar internal functionality to the industry-standard 16C550.
They perform serial-to-parallel conversion on data received from a peripheral device and
parallel-to-serial conversion on data transmitted to the UART. The CPU reads and writes
data and control/status information through the AMBA APB interface. The transmit and
receive paths are buffered with internal FIFO memories that support programmable-ser-
vice 'trigger levels' and overrun protection. These FIFO memories enable up to 16 bytes
to be stored independently in both transmit and receive modes. FIFO depth is 16. If a FIFO
is disabled, a 1-byte holding register is used.
Figure 19-1 shows a block diagram of UART0 and UART1.
nUARTRST
SYSTEM CLOCK
PRESETn
PSEL
PENABLE
PWRITE
PADDR[11:2]
PWDATA[15:0]
PRDATA[15:0]
UARTCLK
UARTRXDMACLR
UARTTXDMACLR
UARTRXDMABREQ
UARTTXDMABREQ
READ
DATA[11:0]
WRITE
DATA[7:0]
16 × 8
TRANSMIT
FIFO
CONTROL AND STATUS
BAUD RATE
APB
DIVISOR
INTERFACE
AND
REGISTER
BLOCK
BAUD
RATE
GENERATOR
REFERENCE CLOCK
FIFO
FLAGS
DMA
INTERFACE
Figure 19-1. UART0 and UART1 Block Diagram
7/15/03
TxD[7:0]
RxD[11:0]
BAUD16
TRANSMIT
RECEIVE
FIFO
FIFO
STATUS
STATUS
INTERRUPT
GENERATION
16 × 12
RECEIVE
FIFO
UARTTXD
TRANSMITTER
UARTRXD
RECEIVER
UARTTXINTR
UARTRXINTR
UARTINTR
LH754xx-13
19-1
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