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Chapter 14
Liquid Crystal
Display Controller
The Liquid Crystal Display (LCD) Controller information in this section pertains to the
LH75400 and LH75410 SoC devices only.
The LCD Controller (LCDC) is an AMBA master-slave module that connects to the AHB.
The LCDC translates pixel-coded data into the required formats and timings to drive
single/dual monochrome LCD panels. The LCDC supports STN LCD displays.
Packets of pixel-coded data are fed, via the AHB interface, to two independently program-
mable, 32-bit-wide DMA FIFOs. Each FIFO is 16 words deep by 32 bits wide. In single-
panel STN Mode, the LCD DMA FIFOs are made to appear as a single FIFO of twice the
size. The buffered pixel-coded data is then unpacked via a pixel serializer. Depending on
the LCD type and mode, the unpacked data can represent either an actual true display
value or an address to a 256 × 16-bit-wide palette RAM value. For STN displays, this value
is passed to the gray-scaling generator.
The LCDC generates a single combined interrupt to the VIC when any of the individual
interrupt conditions becomes true for upper/lower panel DMA FIFO underflow, base
address update signification, vertical compare, or bus error.
6/17/03
14-1
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