Status Register; Table 16-6. Str Register; Table 16-7. Str Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

16.3.1.3 Status Register

STR is the Status Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7
6
5:4
3:0
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 16-7. STR Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
nWDINTR Interrupt Status
nWDINTR
1 = WDT interrupt has triggered.
0 = WDT interrupt has not triggered.
/// Reserved Always reads as 1.
Response Status Holds the required response as set in CTRL Regis-
RSP ter (described in Section 16.3.1.1). The RSP field is, in fact, two copies of
the RSP bit in the CTRL Register.
/// Reserved Writing to these bits has no effect. Reading returns 0.

Table 16-6. STR Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
0 0 0 0
R R R R
0xFFFE3000 + 0x08
DESCRIPTION
6/17/03
Watchdog Timer
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
/// RSP
1 0 0 0 0
R R R R R
17 16
0 0
R R
1 0
///
0 0
R R
16-5