Receive Command Register; Table 20-41. Rcm Register; Table 20-42. Rcm Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3.2.16 Receive Command Register

Register Bank: 1
RCM is the Receive Command Register. The RCM Register controls the operation of the
receive machine. The active bits used in this register are Write Only.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate
BITS NAME
31:8
7
6
5
4
3
2
1:0
31 30 29 28 27
— — — — —
R R R R R
15 14 13 12 11
///
— — — — —
R R R R R

Table 20-42. RCM Register Definitions

/// Reserved Do not modify. Read as zero.
Receive Enable
RXE
1 = Enables the reception of characters.
Receive Disable
RXDI
1 = Disables the reception of data on RXD pin. RxDI takes priority over RxE in
disabling the reception of characters.
Flush Receive Machine
FRM
1 = Resets the receiver logic, except registers and FIFOs, enables reception, and
unlocks the receive FIFO.
FRF Flush Receive FIFO Setting this bit clears the Rx FIFO.
Lock Rx FIFO
1 = Disables the write mechanism of the Rx FIFO, so that characters subsequent-
ly received are lost (not written to the Rx FIFO). Reception is not disabled and
LFR complete status/event reporting continues.
Use this command in the µLAN Mode to disable loading of characters into the
RxFIFO, until an address match is detected. LRF takes priority over ORF in
locking Rx FIFO.
Open (unlock) Rx FIFO
ORF
1 = Enables (unlocks) the Rx FIFO write mechanism.
/// Reserved Read as zero.

Table 20-41. RCM Register

26 25 24 23
///
— — — —
R R R R
10 9 8 7
RXE RXDI FRM FRF
— — — —
R R R W
0xFFFC2000 + 0x14
.
DESCRIPTION
6/17/03
22 21 20 19 18
— — — — —
R R R R R
6 5 4 3 2
LRF ORF
— — — — —
W W W W W
UART2
17 16
— —
R R
1 0
///
— —
R R
20-27