Icr; Table 19-29. Icr Register; Table 19-30. Icr Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

19.3.1.15 ICR

ICR is the Interrupt Clear Register. The active bits used in this register are Write Only. On
a write of '1', the corresponding interrupt is cleared. A write of '0' has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:15
10
9
8
7
6
5
4
3:0
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 19-30. ICR Register Definitions

NAME
///
OVERRUN ERROR
INTERRUPT CLEAR
BREAK ERROR INTER-
RUPT CLEAR
PARITY ERROR
INTERRUPT CLEAR
FRAMING ERROR
INTERRUPT CLEAR
RECEIVE TIMEOUT
INTERRUPT CLEAR
TRANSMIT INTERRUPT
CLEAR
RECEIVE INTERRUPT
CLEAR
///

Table 19-29. ICR Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
0 0 0 0
W W W W
UART0: 0xFFFC0000 + 0x044
UART1: 0xFFFC1000 + 0x044
Reserved Do not modify.
Overrun Error Interrupt Clear Clears the UARTOEINTR
interrupt.
Break Error Interrupt Clear Clears the UARTBEINTR in-
terrupt.
Parity Error Interrupt Clear Clears the UARTPEINTR
interrupt.
Framing Error Interrupt Clear Clears the UARTFEINTR
interrupt.
Receive Timeout Interrupt Clear Clears the
UARTRTINTR interrupt.
Transmit Interrupt Clear Clears the UARTTXINTR
interrupt.
Receive Interrupt Clear Clears the UARTRXINTR interrupt.
Reserved Do not modify.
7/15/03
UART0 and UART1
22 21 20 19 18
0 0 0 0
R R R R
6 5 4 3
0 0 0 0
W W W R
DESCRIPTION
17 16
0 0 0
R R R
2 1 0
///
0 0 0
R R R
19-23