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LH75400/01/10/11 (Preliminary) User's Guide
14.2.4 Palette RAM
The LCDC includes a 256 × 16-bit dual-port RAM-based palette. The least-significant bit
of the serialized pixel data is used to select between the upper and lower halves of the pal-
ette RAM, based on the Byte Ordering Mode.
• One port of the dual-port palette RAM is used as a Read/Write port and is connected to
the AHB slave interface. Palette entries can be written and verified through this port.
• The second port of the dual-port palette RAM is used as a Read Only port and is con-
nected to the unpacker and grayscaler.
Table 14-3 shows the bit representation of each word in the palette.
14.2.5 Grayscale Algorithm
A patented grayscale algorithm drives monochrome STN panels, providing 15 grayscales.
The grayscaler transforms each 4-bit gray value into a sequence of activity-per-pixel over
several frames, relying somewhat on the display characteristics, to give the representation
of grayscales. See Table 14-4.
Data bit values from the grayscaler are shifted into the register in the upper and lower
panel formatter. Each upper and lower panel formatter consists of a Shift Left Register.
When enough data is available, a byte is constructed by multiplexing the registered data
to the correct bit position to satisfy the data pattern of the LCD panel. The byte is trans-
ferred to the FIFO, which has space to store eight pixels.
Table 14-3. Palette Data Storage
BIT
NAME
DESCRIPTION
31:21
///
Reserved
20:17 R[3:0] Grayscale data
16:5
///
Reserved
4:1
R[3:0] Grayscale data
0
///
Reserved
6/17/03
Liquid Crystal Display Controller
14-5
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