Timer 1 Status Register; Table 15-22. Status Register; Table 15-23. Status Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

15.2.2.10 Timer 1 Status Register

The Status Register status bits are independent of the individual interrupt enables. They
are set to 1 upon all compare, capture, and overflow occurrences. To clear the status bits,
write 1s to the individual bits. This action clears the bit that was set in the register and
clears the corresponding interrupt, with the following exception. If the timer is stopped and
the Timer 1 Compare Register (CMP0 or CMP1) value matches the Timer 1 Counter Reg-
ister (CNT), the corresponding status bit cannot be cleared until either the Timer 1 Com-
pare Register or the Timer 1 Counter Register value is changed.
Writing a 0 to a status bit does not affect the corresponding interrupt. Similarly, writing a 1
to a bit that is not set does not affect the Status Register or Interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR

Table 15-22. Status Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 15-23. Status Register Definitions

BITS FIELD NAME
31:5 ///
4 CAP1_ST
3 CAP0_ST
2 CMP1_ST
1 CMP0_ST
0 OVF_ST
26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0
R R R R
0xFFFC4000 + 0x38
DESCRIPTION
Reserved Read as zero.
Timer 1 Capture 1 Status To clear, write 1.
Timer 1 Capture 0 Status To clear, write 1.
Timer 1 Compare 1 Status To clear, write 1.
Timer 1 Compare 0 Status To clear, write 1.
Timer 1 Overflow Status To clear, write 1.
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
0 0 0 0 0
R R RW RW RW
Timers
17 16
0 0
R R
1 0
0 0
RW RW
15-21