Receive / Transmit Fifo Register; Table 18-7. Dr Register; Table 18-8. Dr Register Definitions - Sharp Blue Treak LH75400 User Manual

Synchronous Serial Port

18.5.2.3 Receive / Transmit FIFO Register

DR is the 16-bit-wide Receive / Transmit FIFO register. The active The active bits used in
this register are Read/Write.
• When DR is read, the entry in the receive FIFO (pointed to by the current FIFO read
pointer) is accessed. As data values are removed by the SSP's receive logic from the
incoming data frame, they are placed into the entry in the receive FIFO (pointed to by
the current FIFO write pointer).
• When DR is written to, the entry in the transmit FIFO (pointed to by the write pointer), is
written to. Data values are removed from the transmit FIFO one value at a time by the
transmit logic. Each value is loaded into the transmit serial shifter, then serially shifted
out onto the SSPTX pin at the programmed bit rate.
When a data size of less than 16 bits is selected, programmers must right-justify data writ-
ten to the transmit FIFO. The transmit logic ignores the unused bits. Received data less
than 16 bits is automatically right-justified in the receive buffer.
When the SSP is programmed for National Microwire frame format, the default size for
transmit data is eight bits (the most-significant byte is ignored). The receive data size is
controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared,
even when the SSE bit in Control Register 1 is set to zero (refer to Section 18.5.2.2). This
allows the software to fill the transmit FIFO before enabling the SSP.
When using Texas Instruments mode with data lengths smaller than 16 bits, the most-
significant bits (MSB[s]) that exceed the data length are undefined. As a result, all bits
greater than the length of the data should be masked.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:16
15:0
18-14
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 18-8. DR Register Definitions

/// Reserved Writing to these bits has no effect. Reading returns 0.
Transmit/Receive FIFO
Read = Receive FIFO
Write = Transmit FIFO
DATA
Right-justify data when the SSP is programmed for a data size that is less than
16 bits. Unused bits at the top are ignored by transmit logic. The receive logic
automatically right-justifies.
LH75400/01/10/11 (Preliminary) User's Guide

Table 18-7. DR Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
DATA
0 0 0 0
RW RW RW RW
0xFFFC6000 + 0x008
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R R
1 0
0 0
RW RW