Liquid Crystal Display Controller
14.3.2.12 LCD Palette Register
The color map in the SoC is 65,535 colors. These are mapped into a group of palette
entries, comprising the Palette Registers. The upper four bits of each palette entry is used
for best contrast. The palette is organized as seen in Table 14-29.
Palette Registers contain 256 palette entries organized as 128 locations of two entries per
word. STN monochrome displays use 8 of the palette entry bits, yielding 16 grayscale
shades. Each word location contains two palette entries.
The LH75400 and LH75410 support only monochrome displays; the register locations and
data bits for the Red portions of the palette are used to create and display the monochrome
signals. The Blue and Green portions of the palette are reserved. Writing to them will not
allow creation of color signals for a color display. Note that the palettes are accessed 32
bits at a time.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
14.3.3 LCDC Interrupts
The single combined interrupt, CLCDINTR, drives the VIC. If any of the four interrupt con-
ditions occurs, this signal is asserted.
Each of the four individual maskable interrupt conditions is enabled or disabled by chang-
ing the mask bits in the INTRENABLE Register. Provision of individual outputs, along with
a combined interrupt output, allows the use of either a global interrupt service routine or
modular device drivers to handle interrupts. The status of the individual interrupt sources
can be read from the Status Register.
14-20
Table 14-29. Palette Register
31
30
29
28
27
—
—
—
—
—
RW
RW
RW
RW
RW
15
14
13
12
11
—
—
—
—
—
RW
RW
RW
RW
RW
Table 14-30. Palette Register Definitions
BIT
31:21
20:17
16:5
4:1
0
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
///
—
—
—
—
RW
RW
RW
RW
10
9
8
7
///
—
—
—
—
RW
RW
RW
RW
0xFFFF4000 + 0x200 to 0xFFFF4000 + 0x3FC
NAME
DESCRIPTION
///
Reserved
R[3:0]
Grayscale data
///
Reserved
R[3:0]
Grayscale data
///
Reserved
6/17/03
22
21
20
19
18
RED PALETTE
—
—
—
—
—
RW
RW
RW
RW
RW
6
5
4
3
2
RED PALETTE
—
—
—
—
—
RW
RW
RW
RW
RW
17
16
///
—
—
RW
RW
1
0
///
—
—
RW
RW