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LH75400/01/10/11 (Preliminary) User's Guide
22.3.2.16 Receive Buffer Descriptor Field
Table 22-32 and Table 22-33 show the bit layout of the Descriptor Field of the Receive
Buffer. Table 22-32 shows the SFF message format, while Table 22-33 shows the EFF
message format.
CAN OFFSET
0x40
0x44
0x48
CAN OFFSET
0x40
0x44
0x48
0x4C
0x50
NOTE: The received data length code in the frame information byte (CAN Offset 0x40)
22.3.2.17 Acceptance Code Registers
Registers ACR0, ACR1, ACR2, and ACR3 are the Acceptance Code Registers. These 8-
bit registers record the bit patterns used by the Acceptance Filter, along with the masks
provided by the Acceptance Mask Registers, to filter received data.
The way in which these bit patterns are applied depends on whether a single filter or dual
filters are used and on whether the data is in SFF or EFF format (see Section 22.3.4).
The registers are only accessible for Read/Write access in Reset Mode.
22.3.2.18 Acceptance Mask Registers (AMR0 - AMR3)
Registers AMR0, AMR1, AMR2, and AMR3 are the Acceptance Mask Registers. These
8-bit registers record the mask patterns applied by the Acceptance Filter when filtering
received data. Register values of zero identify the bits of the incoming data bytes that are
required to match the bit values in the corresponding Acceptance Code Registers. Regis-
ter values of 1 mark the bits as 'don't care'.
The bits of incoming data identified by these masks is based on whether:
• A single filter or dual filters are being used
• The data is in SFF or EFF format (see Section 22.3.4).
The registers are only accessible for Read/Write access in Reset Mode.
Table 22-32. Receive Frame (SFF)
BIT 7
BIT 6
FF
RTR
ID.28
ID.27
ID.20
ID.19
Table 22-33. Receive Frame (EFF)
BIT 7
BIT 6
FF
RTR
ID.28
ID.27
ID.20
ID.19
ID.12
ID.11
ID.4
ID.3
represents the length of the data sent, which may be greater than eight bytes.
However, the maximum number of data bytes received will be eight.
BIT 5
BIT 4
BIT 3
0
0
DLC.3
ID.26
ID.25
ID.24
ID.18
RTR
BIT 5
BIT 4
BIT 3
0
0
DLC.3
ID.26
ID.25
ID.24
ID.18
ID.17
ID.16
ID.10
ID.9
ID.8
ID.2
ID.1
ID.0
6/17/03
Controller Area Network
BIT 2
BIT 1
DLC.2
DLC.1
ID.23
ID.22
0
0
0
BIT 2
BIT 1
DLC.2
DLC.1
ID.23
ID.22
ID.15
ID.14
ID.7
ID.6
RTR
0
BIT 0
DLC.0
ID.21
0
BIT 0
DLC.0
ID.21
ID.13
ID.5
0
22-27
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