LH75400/01/10/11 (Preliminary) User's Guide
19.3.1.6 Fractional Baud Rate Divisor Register
FBRD is the fractional part of the baud rate divisor value. The active bits used in this reg-
ister are Read/Write. All the bits are cleared to '0' on System Reset. All the bits are cleared
to '0' on System Reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:16
5:0
Table 19-13. FBRD Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
Table 19-14. FBRD Register Definitions
NAME
///
Reserved Read as zero.
Fractional Baud Rate Divisor This value is used with the Integer Baud
Rate Divisor to ascertain the baud rate for the UART. For information
BAUD RATE
about calculating this divisor value, see Section 19.3.1.7. For information
FUNCTION
about the Integer Baud Rate Divisor, see Section 19.3.1.5. These bits are
cleared to '0' on Reset.
26
25
24
23
///
0
0
0
0
R
R
R
R
10
9
8
7
///
0
0
0
0
RW
RW
RW
RW
UART0: 0xFFFC0000 + 0x028
UART1: 0xFFFC1000 + 0x028
DESCRIPTION
7/15/03
UART0 and UART1
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
BAUD RATE FUNCTION
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
R
R
1
0
0
0
RW
RW
19-13