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Direct Memory Access Controller
12.3.2.8 Interrupt Mask Register
The Interrupt Mask Register selects the status flag that can generate an interrupt. When
exiting Reset, the default value is 0x00. The active bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
12-12
Table 12-8. Interrupt Mask Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
///
0
0
0
0
0
R
R
R
R
R
Table 12-9. Interrupt Mask Register Definitions
BIT
NAME
31:8
///
Reserved Read as zero. Do not write.
Data Stream3 Error Interrupt
7
MaskE3
0 = Disables data stream3 error interrupt.
1 = Enables data stream3 error interrupt.
Data Stream2 Error Interrupt
6
MaskE2
0 = Disables data stream2 error interrupt.
1 = Enables data stream2 error interrupt.
Data Stream1 Error Interrupt
5
MaskE1
0 = Disables data stream1 error interrupt.
1 = Enables data stream1 error interrupt.
Data Stream0 Error Interrupt
4
MaskE0
0 = Disables data stream0 error interrupt.
1 = Enables data stream0 error interrupt.
Data Stream3 Interrupt
3
Mask3
0 = Disables data stream3 interrupt.
1 = Enables data stream3 interrupt.
Data Stream2 Interrupt
2
Mask2
0 = Disables data stream2 interrupt.
1 = Enables data stream2 interrupt.
Data Stream1 Interrupt
1
Mask1
0 = Disables data stream1 interrupt.
1 = Enables data stream1 interrupt.
Data Stream0 Interrupt
0
Mask0
0 = Disables data stream0 interrupt.
1 = Enables data stream0 interrupt.
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
22
///
0
0
0
0
R
R
R
R
R
10
9
8
7
0
0
0
0
R
R
R
RW
RW
0xFFFE1000 + 0x0F0
FUNCTION
7/15/03
21
20
19
18
0
0
0
0
0
R
R
R
R
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
17
16
0
0
R
R
1
0
0
0
RW
RW
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