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LH75400/01/10/11 (Preliminary) User's Guide
13.2.3 How Pixels are Stored in Memory
Table 13-2 and Table 13-3 show the data structure in each DMA FIFO word corresponding
to the bpp combinations. The required data for each panel display pixel must be extracted
from the data word. The first pixel value in the frame corresponds to the color value encoded
in P0, the second corresponds to P1, the third to P2, and so on. This structure is the same
for TFT and STN, except for 12 bpp. Table 13-1 shows the pixel arrangement on a display,
with the first 32 pixels labeled p0 through p31.
bpp
1
p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16
2
4
8
12
(TFT)
12
(STN)
bpp
1
2
4
8
12
(TFT)
12
(STN)
Table 13-1. Pixel Display Arrangement
Table 13-2. Frame Buffer Pixel Storage Format [31:16]
31
30
29
28
27
p15
p14
1
0
1
0
1
p7
3
2
1
0
3
p3
7
6
5
4
3
11
10
9
11
10
9
8
Table 13-3. Frame Buffer Pixel Storage Format [15:0]
15
14
13
12
p15
p14
p13
p12
p7
p6
1
0
1
0
p3
3
2
1
0
p1
7
6
5
4
11
10
11
10
9
Color Liquid Crystal Display Controller
DMA FIFO OUTPUT BITS
26
25
24
23
p13
p12
p11
0
1
0
1
p6
2
1
0
3
2
1
0
7
p1
8
7
6
p1
7
6
5
DMA FIFO OUTPUT BITS
11
10
9
8
p11
p10
p9
p8
p5
p4
1
0
1
0
p2
3
2
1
0
3
2
1
0
p0
9
8
7
p0
8
7
6
7/15/03
22
21
20
19
18
p10
p9
0
1
0
1
p5
2
1
0
3
p2
6
5
4
3
5
4
3
4
3
2
7
6
5
4
3
p7
p6
p5
p4
p3
p3
p2
p1
1
0
1
0
1
p1
3
2
1
0
3
p0
7
6
5
4
3
6
5
4
3
5
4
3
2
17
16
p8
0
1
0
p4
2
1
0
2
1
0
2
1
0
1
0
2
1
0
p2
p1
p0
p0
0
1
0
p0
2
1
0
2
1
0
2
1
0
1
0
13-5
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