Timer 0 Compare/Capture Control Register; Table 15-6. Cmp_Cap_Ctrl Register; Table 15-7. Cmp_Cap_Ctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

15.2.2.2 Timer 0 Compare/Capture Control Register

CMP_CAP_CTRL is the Timer 0 Compare / Capture Control Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15
14
13:12 CMP1
11:10 CMP0

Table 15-6. CMP_CAP_CTRL Register

31 30 29 28 27
0 0 0 0
R R R R R
15 14 13 12 11
PWM TC CMP1
0 0 0 0
RW RW RW RW RW

Table 15-7. CMP_CAP_CTRL Register Definitions

FIELD
NAME
/// Reserved Read as zero.
PWM Output Allows CTCMP0A to be used as a PWM output. This is done by
properly setting up this bit as well as other bits in this register. Refer to
Section 15.1.1 for a complete explanation.
PWM
0 = Outputs CTCMP0A is normal and works only with the CMP0 Register.
1 = Outputs CTCMP0A is in PWM Mode.
Timer 0 Counter Operation Determines whether the Timer 0 counter is to
operate as either a free running counter or as an interval timer. When set, the
counter clears upon matching the CMP1 Register for Timer 0. This operation is
only available with the CMP1 Register. Refer to Section 15.1.1 for a complete
TC
explanation.
0 = Inhibits counter clear (operates as free running counter).
1 = Clears counter when CNT for Timer 0 and CMP1 for Timer 0 match.
Output Value Select Sets the reference value (at which compare match
should occur) that is to be output to CTCMP0B when the CNT Register for Timer
0 matches the CMP1 Register for Timer 0.
00 = No change occurs to the output CTCMP0B.
01 = Output 0 to CTCMP0B.
10 = Output 1 to CTCMP0B.
11 = Toggle the output to CTCMP0B.
Output Value Select Sets the reference value (at which compare match
should occur) that is to be output to CTCMP0A when the CNT Register for Timer
0 matches the CMP0 Register for Timer 0.
00 = No change occurs to the output CTCMP0A.
01 = Output 0 to CTCMP0A.
10 = Output 1 to CTCMP0A.
11 = Toggle the output to CTCMP0A.
26 25 24 23
///
0 0 0 0 0
R R R R
10 9 8 7
CMP0 CAP4 CAP3
0 0 0 0 0
RW RW RW RW
0xFFFC4000 + 0x04
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
CAP2 CAP1
0 0 0 0 0
RW RW RW RW RW
Timers
17 16
0 0
R R
1 0
CAP0
0 0
RW RW
15-11