General Interrupt/Bank Register; Table 20-15. Gir Register; Table 20-16. Gir Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3.2.6 General Interrupt/Bank Register

Register Banks: 0, 1, 2, and 3
GIR is the General Interrupt/Bank Register. The GIR Register holds the highest priority
enabled pending interrupt from the GSR Register. This register also holds a pointer to the
current register segment. Writing to this register updates only the Bank bits.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6
5
4
3:1
0
31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
0 0 0 0
R R R R

Table 20-16. GIR Register Definitions

NAME
/// Reserved Do not modify. Read as zero.
Bank 1 Works with bit [5] to indicate the use of a specific type of bank.
Possibilities are:
• 8250A/16450 Compatible Bank (Bank 0)
Bank 1 • General Work Bank (Bank 1)
• General Configuration Bank (Bank 2)
• Baud Rate Generation Configuration Bank (Bank 3)
For more information, see Table 20-17.
Bank 0 Works with bit [6] to indicate the use of a specific type of bank.
Possibilities are:
• 8250A/16450 Compatible Bank (Bank 0)
Bank 0 • General Work Bank (Bank 1)
• General Configuration Bank (Bank 2)
• Baud Rate Generation Configuration Bank (Bank 3)
For more information, see Table 20-17.
/// Reserved Read as zero.
BI2, BI1, BI0 Read Only Bits Decodes six different pending interrupts (see Table 20-18).
/// Reserved Read as one.

Table 20-15. GIR Register

26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0 0
R R R R R
0xFFFC2000 + 0x08
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
/// BI2 BI1
0 0 0 0 0
RW RW R R R
UART2
17 16
0 0
R R
1 0
BI0 ///
0 1
R R
20-15