Table 4-30. Interrupt Register; Table 4-31. Interrupt Fields; Masked Interrupt Status Register (Interrupt) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

4.5.3.9 Masked Interrupt Status Register (INTERRUPT)

The INTERRUPT Register is a Read Only register. It is a bit-by-bit logical AND of the
Raw Interrupt Status Register (see Section 4.5.3.8) and the INTREN Register (see
Section 4.5.3.6). Interrupt lines correspond to each interrupt. A logical OR of all interrupts
is provided to the Vectored Interrupt Controller.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:5

Table 4-30. INTERRUPT Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 4-31. INTERRUPT Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Masked AHB Master Error Interrupt
4 MBEIM
1 = Interrupt asserted and enabled
0 = No interrupt
Masked Vertical Compare Interrupt
3 VCIM
1 = Interrupt asserted and enabled
0 = No interrupt
Masked LCD Next Base Address Update Interrupt
2 BUIM
1 = Interrupt asserted and enabled
0 = No interrupt
Masked FIFO Underflow Interrupt
1 FUIM
1 = Interrupt asserted and enabled
0 = No interrupt
0 /// Reserved Reading returns 0. Write the reset value.
Color Liquid Crystal Display Controller
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF4000 + 0x24
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
///
0 0
RO RO
4-33