Table 3-12. Epm Register; Table 3-13. Epm Fields; External Peripheral Mapping Register (Epm) - Sharp LH79524 User Manual

Boot Controller

3.2.4 External Peripheral Mapping Register (EPM)

This register determines which chip selects will have burst accesses to their address
regions converted to a series of non-sequential transfers. The register provides individual
selectability for each of nCS0, nCS1, nCS2, and nCS3. At reset, accesses to all four chip
select regions have conversion enabled. This ensures that all external devices will be
accessible following reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:4
3
2
1
0
3-10
31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
0 0 0 0
RO RO RO RO RO
/// Reserved Reading returns 0. Write the reset value.
nCS3 Configured for External Peripherals
1 = All burst accesses to nCS3 are converted to a series of non-sequential single
CS3EP
transfers.
0 = Accesses to nCS3 are unaltered.
nCS2 Configured for External Peripherals
1 = All burst accesses to nCS2 are converted to a series of non-sequential single
CS2EP
transfers.
0 = Accesses to nCS2 are unaltered.
nCS1 Configured for External Peripherals
1 = All burst accesses to nCS1 are converted to a series of non-sequential single
CS1EP
transfers.
0 = Accesses to nCS1 are unaltered.
nCS0 Configured for External Peripherals
1 = All burst accesses to nCS0 are converted to a series of non-sequential single
CS0EP
transfers.
0 = Accesses to nCS0 are unaltered.

Table 3-12. EPM Register

27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFE6000 + 0x08

Table 3-13. EPM Fields

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 1
RO RO RO RW RW
17 16
0 0
RO RO
1 0
1 1
RW RW