Dma Interface - Sharp LH79524 User Manual

Universal Serial Bus Device

17.1.4 DMA Interface

The USB Device includes a six channel DMA Controller with a 64-byte buffer. This section
describes the DMA operation and gives programming examples.
17.1.4.1 DMA Modes
The DMA controller supports two modes of operation. The operating mode of each
channel can be programmed independently.
• DMA Mode 0: DMA Mode 0 can be used with any endpoint, whether it uses Control,
Bulk, Isochronous, or Interrupt transactions. In this mode, the DMA controller can be pro-
grammed to only load/unload one packet, so processor intervention is required for each
packet transferred over the USB.
• DMA Mode 1: DMA Mode 1 can only be used with endpoints that use Bulk transactions. In
this mode, the DMA controller can be programmed to load/unload a complete Bulk transfer
(which can be many packets). Once set up, the DMA controller will load and unload all
packets of the transfer, interrupting the processor when the entire transfer has completed.
17.1.4.2 DMA Bus Cycles
The DMA controller uses incrementing bursts of unspecified length on the AHB. It starts a
new burst when first granted bus mastership (whether at the start of a USB packet or when
regaining the bus after losing it part way through a packet), and when the AHB address
starts a new 1KB block.
When the DMA controller is instructed to load a packet, it requests bus mastership of the
AHB. When granted, the DMA controller reads the AHB until either the entire packet has
been read or the DMA buffer becomes full. It then releases the AHB and begins transfer-
ring the data just read to the selected FIFO. This process is repeated until the entire packet
has been read and loaded into the FIFO.
When the DMA controller is instructed to unload a packet, it reads data from the selected
FIFO into the DMA buffer until either the entire packet has been read or the DMA buffer
becomes full. It then requests bus mastership on the AHB and, when granted, performs
AHB writes until the DMA buffer has been unloaded. This process is repeated until the
entire packet has been unloaded from the FIFO and transferred on the AHB.
If AHB slave access to any of the registers occurs while the DMA controller is either loading
or unloading the FIFO, the DMA controller will stop the transfer while the AHB slave access
is being made, then continue the transfer after the slave access has been completed.
As long as the start address (written to the ADDRx register) is word aligned, all the trans-
fers for a packet will be word transfers (32-bits), with possible half-word and/or byte trans-
fers added at the end to handle any residue. However if the start address is merely half-
word aligned, the DMA controller will use half-word transfers for the duration of the packet,
with a possible byte transfer at the end. If the start address is an odd byte address, the
DMA controller will use byte transfers for the duration of the packet.
17.1.4.3 Bus Errors
If a bus error occurs while the DMA controller is accessing memory on the AHB, the DMA
controller immediately terminates the DMA transfer and interrupts the processor with the
CNTLx:BUS_ERR bit set to 1.
17-4 Version 1.0
LH79524/LH79525 User's Guide