Table 13-37. Ssppre Register; Table 13-38. Ssppre Fields; Table 13-39. Ssppre Register Values; Ssp Clock Prescaler Register (Ssppre) - Sharp LH79524 User Manual

Reset, Clock, and Power Controller

13.2.2.16 SSP Clock Prescaler Register (SSPPRE)

The value in this register is used as a divisor for the Source Clock to derive the SSP clock
(SSPCLK) frequency. The SSP clock source (System Clock Oscillator, or HCLK) is
selected with the PCLKSEL1:SSP bit (see Section 13.2.2.13). Table 13-39 shows the
valid combinations for SSPDIV and the resulting SSP clock frequency. Following reset, the
prescaler is programmed to pass the clock through without division. All other SSPDIV val-
ues are invalid.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
13-26

Table 13-37. SSPPRE Register

31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0
RO RO RO RO RO

Table 13-38. SSPPRE Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
SSP Divisor Program with the clock source divisor for the SSP Clock
SSPDIV
prescaler (see Table 13-39).

Table 13-39. SSPPRE Register Values

SSPDIV
0b00000000 (default)
0b00000001
0b00000010
0b00000100
0b00001000
0b00010000
0b00100000
0b01000000
0b10000000
26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0 0
RO RO RO RW
0xFFFE2000 + 0x44
DESCRIPTION
DIVISOR
1
2
4
8
16
32
64
128
256
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
SSPDIV
0 0 0 0 0
RW RW RW RW RW
ƒ(SSP)
ƒ(clock source)
ƒ(clock source)/2
ƒ(clock source)/4
ƒ(clock source)/8
ƒ(clock source)/16
ƒ(clock source)/32
ƒ(clock source)/64
ƒ(clock source)/128
ƒ(clock source)/256
17 16
0 0
RO RO
1 0
0 0
RW RW