Table 5-33. Status Register; Table 5-34. Status Fields - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
5.2.2.10 Status Register (STATUS)
The STATUS Register provides status information about the DMA Controller interrupts.
The interrupt status bits are cleared by writing to the CLR register.
The INT[3:0] bits are the data stream interrupt flags corresponding to data stream 0
through data stream 3. A data stream sets its corresponding interrupt flag when a data
transfer is completed (a complete packet has been transferred to its destination).
The ERRORINT[3:0] bits are the Error interrupts corresponding to data stream 0 through
data stream 3. An error interrupt status is set when its corresponding data stream's transfer
aborts due to an AHB transfer error. When this occurs, the stream is disabled until software
sets the Enable bit again.
The Active flags indicate whether a data stream is transferring data. It is HIGH if a data
transfer is in progress. The Active flags have the same polarity as the Enable bits in the
Data Stream Control Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:12
11
10
9
8

Table 5-33. STATUS Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 5-34. STATUS Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Data Stream 3 Active/Inactive
ACTIVE3
1 = Data stream 3 is active
0 = Data stream 3 is not active
Data Stream 2 Active/Inactive
ACTIVE2
1 = Data stream 2 is active
0 = Data stream 2 is not active
Data Stream 1 Active/Inactive
ACTIVE1
1 = Data stream 1 is active
0 = Data stream 1 is not active
Data Stream 0 Active/Inactive
ACTIVE0
1 = Data stream 0 is active
0 = Data stream 0 is not active
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RO RO RO
0xFFFE1000 + 0x0F8
DESCRIPTION
Version 1.0
Direct Memory Access Controller
22 21 20 19 18
0 0 0 0
RO RO RO RO RO
6 5 4 3
INT3 INT2 INT1 INT0
0 0 0 0
RO RO RO RO RO
17 16
0 0 0
RO RO
2 1 0
0 0 0
RO RO
5-17