Table 6-3. Pause Frame Support - Sharp LH79524 User Manual

Ethernet MAC Controller
The Back-Off Time is based on an Exclusive OR of the 10 least-significant bits of the data
stream from the transmit FIFO and a 10-bit pseudo-random number generator. The num-
ber of bits used depends on the number of collisions seen. After the first collision one bit
is used, the second two, and so on up to 10. For more than 10, all 10 bits are used. If 16
attempts cause collisions, an error is indicated and no further attempts will be made.
If transmit DMA underruns, bad CRC is automatically appended using the same mecha-
nism as jam insertion and the Transmit Error (ETHERTXER) pin is asserted. For a properly
configured system this should never happen.
If the NETCTL:BACKPRESS bit is set in half-duplex mode, the transmit block will transmit
64 bits of data, which can consist of 16 nibbles of 1011, or in bit-rate mode, 64 consecutive
1s, whenever it sees an incoming frame to force a collision. This provides a way of imple-
menting flow control in half-duplex mode.
6.1.4.1 Pause Frame Support
The start of an 802.3 pause frame follows the format in Table 6-3.
DESTINATION
ADDRESS
0x0180C2000001
If a valid pause frame is received, the Pause Time register (PAUSETIME) is updated with
the frame's pause time regardless of its current contents, and regardless of the state of the
NETCONFIG:PAUSEEN bit. An interrupt is asserted when a pause frame is received,
assuming it is enabled in the Interrupt Mask register. If NETCONFIG:PAUSEEN
the value of the PAUSETIME register is non-zero, no new frame is transmitted.
A valid pause frame has a destination address that matches either the address stored in
Specific Address Register 1 (SPECAD1BOT and SPECAD1TOP) or matches
0x0180C2000001, has a MAC Control Frame Type ID of 0x8808, and has the Pause
Opcode of 0x0001.
Pause frames that have FCS or other errors are treated as invalid and discarded. Valid pause
frames received increment the Pause Frame Received statistics register (PAUSEFRRX).
The PAUSETIME register decrements every 512 bit times once transmission has stopped.
For test purposes, the register decrements every Receive Clock cycle once transmission
has stopped if NETCONFIG:RETRY is 1. If the NETCONFIG:PAUSEEN is not 1, decre-
menting occurs whether transmission has stopped or not. An interrupt is asserted when-
ever the PAUSETIME register decrements to zero (assuming the interrupt is enabled in
the MASK register).
6-10

Table 6-3. Pause Frame Support

SOURCE
ADDRESS (MAC CONTROL FRAME)
6 bytes 0x8808
Version 1.0
LH79524/LH79525 User's Guide
TYPE PAUSE
OPCODE
0x0001
PAUSE
TIME
2 bytes
and
is 1