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External Memory Controller
7.2.4.2 Bus Turnaround
The EMC can be configured for each memory bank to use external bus turnaround cycles
between read and write memory accesses. The STURNx register can be programmed for
1 to 16 bus-turnaround wait states to avoid contention on the external data bus. Bus turn-
around cycles are generated between external bus transfers: Read to Read (different mem-
ory banks), Read to Write (same memory bank), Read to Write (different memory banks).
7.2.4.3 Byte Lane Control
The EMC generates signals nBLE[3:0] according to:
• Internal memory transfer
• External memory bank data bus width, defined within each Control register
• Decode HADDR[1:0] for write accesses only.
Word transfers (32-bit) are the largest size transfers supported by the memory controller.
Any access attempted with a size greater than a word causes an ERROR response to
be generated. Each memory Chip Select space can be 8, 16, or 32 bits wide. The type of
memory used determines how the nWE and nBLEx signals are connected to provide byte,
half-word and word access. For read accesses, the nBLEx signals must be either all HIGH,
or all LOW. This is done by programming the Byte Lane State (BLS) bit in the SCONFIG
register (SCONFIG:BLS).
7.2.4.4 Write Protection
Each static memory Chip Select space can be configured for write-protection. Usually
SRAM is unprotected and ROM devices must be write-protected (to avoid potential bus
conflict when performing a write access to ROM), the SCONFIG:P field can be set to write-
protect SRAM as well as ROM devices.
7.2.4.5 nWAIT Transfers
The EMC's Static Memory Controller supports an nWAIT input that can be used by an
external device to extend the wait time during a memory access. The SMC samples nWAIT
at the beginning of each system clock cycle. The system clock cycle in which the nCSx
signal is asserted counts as the first wait state. Timing diagrams and extensive descrip-
tions appear the the LH79524/LH79525 Data Sheet.
7-16
Version 1.0
LH79524/LH79525 User's Guide
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