Table 10-2. Ctrl Register; Table 10-3. Ctrl Register Definitions; Register Descriptions - Sharp LH79524 User Manual

2
I S Converter

10.2.2 Register Descriptions

Note that SSP register bits duplicated in the I
bit by one clock.
10.2.2.1 Control Register (CTRL)
This register allows control of various I
inversion, WS control, enabling the converter and selecting its mode.
of the functions apply only to
not active. Explanation of the 'WS' function appears following Table 10-3.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:6
5
4 CLKINV
3 WSDEL
2
1
0
10-14
31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
0 0 0 0
RO RO RO RO RO

Table 10-3. CTRL Register Definitions

NAME
/// Reserved Reading returns 0. Write the reset value.
Loopback Mode Applies only to I
still be received in master mode.
LOOP
1 = Transmit and Receive internally connected for Loopback Mode
0 = Normal operation
Clock Invert Applies only to I
I2SCLK, which is output on the PB3SSPCLK/I2SCLK pin.
1 = Invert SSPCLK/I2SCLK
0 = Do not invert SSPCLK/I2SCLK
WS Delay Applies only to I
1 = WS transitions with MSB (left justified)
0 = WS transitions one clock before MSB (I
WS Invert Applies only to I
WSINV
1 = Invert the function of WS (first sampled driven/latched will have WS = 1)
0 = No change in function of WS (first sampled driven/latched will have WS = 0)
2
Enable I S Converter When this bit is 0, the registers in the I
are cleared, and the master and slave clock inputs are gated off.
I2SEN
2
1 = Enable I S converter, convert between SSP mode and I
2
0 = Disable I S converter, pass through SSP signals unchanged
2
I S Select
I2SEL
2
1 = I S functions are selected
0 = SSP functions are selected
2
S Converter will lag the SSP version of the
2
S Converter functions, including Loopback, clock
2
transactions; for SSP transactions, those bits are
I S

Table 10-2. CTRL Register

27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFC8000 + 0x000
DESCRIPTION
2
S Transactions. Note that two frames of 0x0000 will
2
S Transactions. Inverts the polarity of the SSPCLK or
2
S Transactions
2
2
S Transactions (see Table 10-6)
Version 1.0
LH79524/LH79525 User's Guide
Notice that some
22 21 20 19
0 0 0 0
RO RO RO RO
6 5 4 3
0 0 0 0
RO RW RW RW
S justified)
2
S data and frame paths
2
S formats
18 17 16
0 0 0
RO RO RO
2 1 0
0 0 0
RW RW RW