Table 16-22. Uartcr Register; Table 16-23. Uartcr Fields; Uart Control Register (Uartcr) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

16.3.2.8 UART Control Register (UARTCR)

UARTCR is the UART Control Register. To enable transmission, bit [8] and bit [0] must be
set. Similarly, to enable reception, bit [9] and bit [0] must be set.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:10
15
14
12:13
11
10
9

Table 16-22. UARTCR Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
/// RTS
0 0 0 0 0
RW RW RW RW RW

Table 16-23. UARTCR Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
CTS Hardware Flow Control Enable (CTSEN) This bit enables CTS hard-
ware flow control. Data is only transmitted when the nUARTCTS signal is as-
serted. (Only used with UART0)
CTSEN
1 = CTS hardware flow control enabled
0 = CTS hardware flow control disabled
RTS Hardware Flow Control Enable (RTSEN) This bit enables RTS hard-
ware flow control. Data is only requested when there is space in the receive
FIFO for it to be received. (Only used with UART0)
RTSEN
1 = RTS hardware flow control is enabled
0 = RTS hardware flow control disabled
/// Reserved Reading returns 0. Write the reset value.
Request to Send (RTS) This bit is the complement of the request to send
(nUARTRTS) modem status output. (Only used with UART0)
RTS
1 = The output is 0
0 = The output is 1
Reserved Do not modify. When writing to this register, perform a
///
read-modified-write operation to this bit.
Receive Section Enables the receive section of the UART.
1 = Receive section enabled. When the UART is disabled in the middle of
RXE
reception, it completes the current character before stopping
0 = Receive section not enabled
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
/// RXE TXE LBE
0 1 1 0
RW RW RW RW
UART 0: 0xFFFC0000 + 0x030
UART 1: 0xFFFC1000 + 0x030
UART 2: 0xFFFC2000 + 0x030
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
///
0 0 0 0 0
RW RW RW RW RW
UARTs
17 16
0 0
RO RO
1 0
0 0
RW RW
16-17