Table 2-27. Mis Register; Table 2-28. Mis Fields; Masked Interrupt Status Register (Mis) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

2.2.2.13 Masked Interrupt Status Register (MIS)

MIS is the Masked Interrupt Status register. This Read Only register gives the masked
value of each interrupt. The BROWNOUT, PENSYNC, and EOS interrupts are latched and
must be cleared by writing to the Interrupt Clear (IC) register. The FWATER and FOVRN
interrupts are cleared when the contents of the FIFO no longer exceed their thresholds.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0
RO RO RO RO RO
BIT NAME
31:5 /// Reserved Reading returns 0. Write the reset value.
Brown-Out Interrupt Status
4 BROWNOUT
1 = Brown-out Interrupt is asserted
0 = Brown-out Interrupt is not active or not enabled
Pen Interrupt Status
3 PENSYNC
1 = Pen Interrupt is asserted
0 = Pen Interrupt is not active or not enabled
End-of-Sequence Interrupt Active
2 EOSINTR
1 = EOSIA Interrupt is asserted
0 = EOSIA Interrupt is not active or not enabled
FIFO Watermark Interrupt Active
1 FWATERINTR
1 = FIFO Watermark Interrupt is asserted
0 = FIFO Watermark Interrupt is not active or not enabled
FIFO Overrun Interrupt Active
0 FOVRNINTR
1 = FIFO Overrun Interrupt is asserted
0 = FIFO Overrun Interrupt is not active or not enabled
Analog-to-Digital Converter/Brownout Detector

Table 2-27. MIS Register

26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFC3000 + 0xAC

Table 2-28. MIS Fields

DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO
2-25