LH79524/LH79525 User's Guide
6.3.3.19 SQE Test Errors (SQERR)
This 8-bit register contains the number of frames where the ETHERCOL pin was not
asserted within 96 bit times (one inter-frame gap) of the ETHERTXEN pin being deas-
serted in half-duplex mode.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:8
7:0
6.3.3.20 Received Length Field Mismatch (RXLEN)
This register counts the number of received frames that have a measured length shorter
than specified in its length field. Checking is enabled via the NETCONFIG:LENGTHCHK
bit. Frames containing a type ID in bytes 13 and 14 (length/type ID ≥ 0x0600) will not be
counted as length field errors, nor will excessive length frames.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS NAME
31:8
7:0
Table 6-70. SQERR Register
31
30
29
28
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
///
0
0
0
0
RO
RO
RO
RO
RO
NAME
///
Reserved Reading returns 0. Write the reset value.
SQE Test Errors Shows the number of frames where the ETHERCOL pin was
SQERR
not asserted within 96 bit times
31
30
29
28
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
///
0
0
0
0
RO
RO
RO
RO
RO
///
Reserved Reading returns 0. Write the reset value.
Receive Length Field Mismatch Contains the number of received frames that
RXLEN
have a measured length shorter than that extracted from its length field.
27
26
25
24
23
///
0
0
0
0
0
RO
RO
RO
RO
11
10
9
8
7
0
0
0
0
0
RO
RO
RO
RW
0xFFFC7000 + 0x84
Table 6-71. SQERR Fields
FUNCTION
Table 6-72. RXLEN Register
27
26
25
24
23
///
0
0
0
0
0
RO
RO
RO
RO
11
10
9
8
7
0
0
0
0
0
RO
RO
RO
RW
0xFFFC7000 + 0x88
Table 6-73. RXLEN Fields
FUNCTION
Version 1.0
Ethernet MAC Controller
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
SQERR
0
0
0
0
0
RW
RW
RW
RW
RW
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
RXLEN
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW
17
16
0
0
RO
RO
1
0
0
0
RW
RW
6-47