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Chapter 15
Timers
The LH79524 and LH79525 both have three 16-bit timers:
• Timer 0 has five Capture Registers and two Compare Registers.
• Timer 1 has two Capture Registers and two Compare Registers.
• Timer 2 has two Capture Registers and two Compare Registers.
Throughout this chapter, all descriptions apply to both the LH79524 and LH79525. In this
chapter there are also a number of registers with similar names and functions. Descrip-
tions of these registers refer to the name with an 'x' replacing the timer number, for exam-
ple a reference to the CTRLx register refers to all three Timer Control Registers (CTRL0,
CTRL1, and CTRL2). In some instances, such as the Timer Capture Registers, 'x' repre-
sents the timer number, and 'n' represents the lettered or numbered register suffix. For
example, TxCAPn would represent all the Timer Capture Registers; T1CAPn would repre-
sent all the Timer 1 Capture Registers; T1CAPA is the specific register.
The timers are clocked by HCLK, but scaled down internally for use in the PWM and com-
pare functions. All counters are incremented by an internal prescaled counter clock or
external clock and can generate an overflow interrupt when the counter increments from
0xFFFF to 0x0000. All three timers have separate internal prescaled counter clocks, with
either a common external clock (CTCLK) or a prescaled version of HCLK.
All Capture Registers have edge-selectable inputs and can generate an interrupt, if
desired. Each timer can also generate a separate interrupt, which is asserted if any
enabled compare, capture, or overflow interrupt condition occurs. The interrupt remains
active until all compare, capture, and overflow interrupts are cleared. Each Compare Reg-
ister can force its associated compare output pin either HIGH or LOW upon a match.
Figure 15-1 shows a block diagram of the three timers.
Version 1.0
15-1
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