Figure 4-4. Lcd Panel Power Sequencing; Lcd Power Sequencing At Turn-On And Turn-Off - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

4.3.9 LCD Power Sequencing at Turn-On and Turn-Off

Many LCD panels require ground, power for the digital logic, and high-voltage power sup-
plies. To extend the life of these panels, the digital power must be applied before the high
voltage is applied, and removed after they are removed. The logic signals driving the panel
must be active before the panel voltages are applied, and the panel voltages must be
removed before the logic signals are removed. This sequencing ensures that the panel is
always operated with a net DC bias of 0 VDC.
Software must ensure that these conditions are met. The requisite delay is usually speci-
fied in the LCD panel's data sheet. If the proper power sequencing is not followed, the LSI
drivers in the panel can latch and the display will freeze. Typically when this happens, the
colors will be incorrect on STN panels. In addition the power down sequence must be fol-
lowed or LCD life can be degraded.
Figure 4-4 is an example of these timing requirements for the SHARP LM057QCTT03
Color STN LCD Panel, and the accompanying timing specifications. Always refer to your
specific LCD panel's Data Sheet to determine the specific turn-on and turn-off require-
ments for the panel being used in your application.
YD, LP,
XCK, DATA
DISP
NOTE: 500 ms MIN. ON/OFF cycle time. All signals and power must be
Note
tVLD
VDD
tDC
tCR
VEE
tVLVP tVPD
switched in this sequence during power ON/OFF cycles.

Figure 4-4. LCD Panel Power Sequencing

Color Liquid Crystal Display Controller
tRDVL
tRCD
tRCVP
tRVPVL
Version 1.0
POWER ON
SYMBOL
ALLOWABLE VALUE
tVLD 0 ms MIN. 1 sec. MAX.
tDC 20 ms MIN.
tCR 100 ns MAX.
tVPD 0 ms MIN.
tVLVP 0 ms MIN.
POWER OFF
SYMBOL ALLOWABLE VALUE
tRDVL 0 ms MIN. 1 sec. MAX.
tRCD 20 ms MIN.
tRCVP
20 ms MIN.
tRVPVL 0 ms MIN.
79525-47
4-15