Extended Wait Transfers - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

7.2.4.6 Extended Wait Transfers

The static memory controller supports extremely long transfer times. In normal use the
memory transfers are timed using the SWAITRDx and SWAITWRx registers. These reg-
isters enable transfers with up to 32 wait states. However, if an extremely slow static mem-
ory device has to be accessed, enable the SCONFIG Extended Wait (EW) bit. When this
bit is enabled the WAIT register is used to time both the read and write transfers. This reg-
ister enables transfers to have up to 16,368 wait states.
NOTES:
1. Using extremely long transfer times might mean that SDRAM devices are not refreshed correctly.
2. Very slow transfers can severely degrade system performance as the external memory interface is tied up
for long periods of time. This has detrimental efforts on time critical services, such as interrupt latency and
low latency devices, for example the CLCDC.
7.3 Interfacing with NAND Flash
The EMC interface for NAND Flash has two modes: one for booting and one for accesses
during normal program execution. During boot, the Boot ROM handles the logic for gener-
ating control signals on the four address lines used for the Address Latch Enable (ALE),
Command Latch Enable (CLE), Flash Write Enable (nFWE), and Flash Read Enable
(nFRE) signals. When used for booting, the NAND Flash must be selected with Chip Select
nCS0, which has been programmed as GPIO PM0. If not used for booting, the NAND
Flash device can be selected with any Chip Select signal. See Chapter 3 and the examples
that follow for more information about the Boot Controller.
7.3.1 Booting Example
Booting from NAND Flash is defined by the static signals on Port C[7:4] at the rising edge
of nRESETOUT, as shown in Table 7-2 and Table 7-3. Whenever PC6 is HIGH, boot
occurs from a NAND Flash (or via I2C or UART, which do not require a Chip Select). Unlike
booting from other devices, NAND Flash must be located in the nCS0 Chip Select domain.
If the application uses the on-board Boot ROM to direct a boot from external NAND Flash,
four address lines function as NAND Flash control pins. Connection of the SoC to the
NAND Flash is illustrated in Figure 7-14.
During boot, the Boot ROM in the LH79524/LH79525 automatically controls the logic to
present the proper signals at the proper times on the address lines acting as control sig-
nals. Thus, care must be taken to either not use nCS0 for other devices, or ensure that the
NAND Flash is not inadvertently accessed by addresses in the nCS0 address space.
In addition, the code in the Boot ROM automatically shifts the addresses, so the control
and address signals appear on the same pins for any width NAND Flash. Thus, the con-
nection diagram in Figure 7-14 shows correct implementation for all memory widths.
Version 1.0
External Memory Controller
7-17