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2
I
S Converter
10.1.5 Suppression of SSPFSSIN
The assertion of SSPFSSIN to the SSP is suppressed under the following conditions:
• When the channel indicated by the Transmit FIFO differs from the channel expected by
the External Codec. Since the I
the channels indicated by the TXFIFO and RXFIFO should always match, so only the
Transmit FIFO is monitored. When the channel in the Transmit FIFO matches the chan-
nel expected by the External Codec, the SSPFSSIN pulse is not suppressed.
• During a Transmit FIFO Underrun. If the I
while the TXFIFO is empty, then the SSP will continually re-transmit whatever data was
last in TXFIFO(0) and indicate the channel associated with TXFIFO(0). Due to the sup-
pression logic described above, every other pulse to the SSP would be suppressed and
the data value transmitted by the SSP would alternate from the last 16-bit value in
TXFIFO(0) and the last bit in the SSP shift register. This violates the requirement that
known data be sent during a TXIFO Underrun. Therefore, asserting SSPFSSIN will be
suppressed during a TXFIFO Underrun while the I
a logic 0 will be fed into the I
data is flushed out, followed by logic 0.
• When the I
The suppression of SSPFSSIN and forcing 0 on the shift register input only occurs when
2
the I
S Converter is enabled in slave mode. If the I
10.1.6 Channel Management
The Word Select (WS) signal from the I
PB2/SSPFRM/I2SWS/IN signal. This signal transitions one SSPCLK_I2SCLK_OUT/IN
before the MSB of a new data item is sent/received and its state describes if the
data is left or right channel. The equivalent TI mode signal, SSPFSSOUT/IN, is a one
SSPCLKOUT/IN long pulse that signals the beginning of data for one clock.
There are several mechanisms to control and report the behavior of the WS signal.
The WS bit may be delayed, with respect to the data, to transition on the same clock as
the MSB of the data via the WSDEL control bit. The function of WS may be inverted via
the WSINV control bit. The value of WS at the pin can be sampled via the WS status bit.
10-10
2
S Converter is assumed to operate in full-duplex mode,
2
S Converter Frame Delay pipe so that any remaining valid
2
S Converter is operating in master mode.
Version 1.0
LH79524/LH79525 User's Guide
2
S Converter asserts SSPFSSIN to the SSP
2
S Converter is enabled. Additionally,
2
S is disabled, the SSP is not altered.
2
S specification is carried on the
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