Slave Mode - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

9.1.3 Slave Mode

In slave-receiver mode, the I
data byte has been received. The sequence is that the byte is received and acknowledged
by the I
data byte, 7-bit Slave address, or one of the two 10-bit Slave address bytes. Status bits in
the ICSTAT register allow the processor to determine the type of transfer.
Whenever data is received, the ICSTAT:FULL bit is set. If the bit remains set, one more
transfer can take place over the interface before the I
ing the master from sending any more bytes and creating an overflow condition. Reading
the ICDATA register clears the bit.
In slave-transmitter mode, the I
received, when the I
START conditions. When the I
FULL bit. This will be cleared when the ICDATA register is written by the processor. In
slave-transmitter mode, the ICCON register must be written for each byte, setting the
ICCON START bit to initiate the transfer.
Interrupts set the ICSTAT INT bit. Before the interrupt routine is exited, this bit must be
cleared by reading the ICSTAT register.
In address and repeat START transactions, reading the ICDATA and ICSTAT registers
is all that is required of the interrupt handler, since address comparisons are performed
in hardware.
9.1.4 Master Mode
Master mode is similar to Slave mode from an interrupt-handling point of view, but the I
Module now transmits rather than receives addresses, and bus arbitration must be per-
formed as well.
Master-mode transactions start by testing ICSTAT IDLE bit to verify that the I
idle, then initiating an address transaction. Address bytes and START bytes are generated
in software and written to the ICDATA register as if they were data.
The handling of individual data interrupts is much the same as in Slave mode.
9.1.5 Resetting a Locked Slave
If transactions on I
machine could be "dead-locked" into a particular state other than idle. Exiting this state
requires issuing a Master Abort command, which is not possible with the I
ever, the interface can be bit-banged using the GPIO function to signal a Master Abort (i.e.,
STOP condition, SCL High, and SDA Rising Edge). This should resolve any (one or many)
peripheral slaves that have entered a dead-lock state. Once this is done, switch back to
2
the I C function and continue to operate as normal.
2
2
C Module, then the processor is interrupted. The ICDATA register will contain a
2
C Module is ready to receive another data byte, and on repeat
2
C have been interrupted, there is the possibility that a slave's state
C Module interrupts the processor whenever an address or
2
C Module interrupts the processor when an address is
2
C Module is ready to send another byte, it sets the ICSTAT
Version 1.0
2
C Module holds SCL LOW, prevent-
2
C module. How-
2
I C Module
2
C
2
C Module is
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