Table 5-31. Clr Register; Table 5-32. Clr Fields; Interrupt Clear Register (Clr) - Sharp LH79524 User Manual

Direct Memory Access Controller

5.2.2.9 Interrupt Clear Register (CLR)

The Interrupt Clear Register clears the status flags. Writing a 1 to a bit clears the interrupt
status bit in the STATUS register. This register has an indeterminate value after Reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:8
5-16
31 30 29 28 27
— — — — —
RO RO RO RO RO
15 14 13 12 11
///
— — — — —
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Clear ErrorInt3 Flag
7 CLEARE3
1 = Clears the ERRORINT3 interrupt flag in the Status Register
0 = No effect
Clear ErrorInt2 Flag
6 CLEARE2
1 = Clears the ERRORINT2 interrupt flag in the Status Register
0 = No effect
Clear ErrorInt1 Flag
5 CLEARE1
1 = Clears the ERRORINT1 interrupt flag in the Status Register
0 = No effect
Clear ErrorInt0 Flag
4 CLEARE0
1 = Clears the ERRORINT0 interrupt flag in the Status Register
0 = No effect
Clear Int3 Flag
3 CLEAR3
1 = Clears the INT3 interrupt flag in the Status Register
0 = No effect
Clear Int2 Flag
2 CLEAR2
1 = Clears the INT2 interrupt flag in the Status Register
0 = No effect
Clear Int1 Flag
1 CLEAR1
1 = Clears the INT1 interrupt flag in the Status Register
0 = No effect
Clear Int0 Flag
0 CLEAR0
1 = Clears the INT0 interrupt flag in the Status Register
0 = No effect

Table 5-31. CLR Register

26 25 24 23
///
— — — —
RO RO RO RO
10 9 8 7
— — — —
RO RO RO WO
0xFFFE1000 + 0x0F4

Table 5-32. CLR Fields

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
— — — — —
RO RO RO RO RO
6 5 4 3 2
— — — — —
WO WO WO WO WO
17 16
— —
RO RO
1 0
— —
WO WO