Table 11-68. Muxctl24 Register; Table 11-69. Muxctl24 Fields; Multiplexing Control 24 Register (Muxctl24) - Sharp LH79524 User Manual

I/O Configuration

11.2.2.34 Multiplexing Control 24 Register (MUXCTL24)

The MUXCTL24 Register allows software to configure a number of LH79524/LH79525 pins.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
11-52

Table 11-68. MUXCTL24 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
/// PH1
0 0 0 0 0
RO RO RW RW RW

Table 11-69. MUXCTL24 Fields

BIT NAME
31:14 /// Reserved Reading returns 0. Write the reset value.
PH1/ETHERRXDV Assignment
00 = PH1
13:12 PH1
01 = ETHERRXDV
10 = Reserved
11 = Reserved
PH0/ETHERRX3 Assignment
00 = PH0
11:10 PH0
01 = ETHERRX3
10 = Reserved
11 = Reserved
PI7/ETHERRX2 Assignment
00 = PI7
9:8 PI7
01 = ETHERRX2
10 = Reserved
11 = Reserved
PI6/ETHERRX1 Assignment
00 = PI6
7:6 PI6
01 = ETHERRX1
10 = Reserved
11 = Reserved
PI5/ETHERRX0 Assignment
00 = PI5
5:4 PI5
01 = ETHERRX0
10 = Reserved
11 = Reserved
PI4/ETHERRXER Assignment
00 = PI4
3:2 PI4
01 = ETHERRXER
10 = Reserved
11 = Reserved
PI3/ETHERCRS Assignment
00 = PI3
1:0 PI3
01 = ETHERCRS
10 = Reserved
11 = Reserved
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
PH0 PI7 PI6
0 0 0 0
RW RW RW RW
0xFFFE5000 + 0xB8
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
PI5 PI4
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
PI3
0 0
RW RW