Sharp LH79524 User Manual page 6

Table of Contents
4.6 Timing Waveforms ......................................................................................... 4-42
Chapter 5 - Direct Memory Access Controller
5.1 Theory Of Operation......................................................................................... 5-2
5.2 Register Reference .......................................................................................... 5-5
iv
4.5.3.3 Clock and Signal Polarity Control Register (TIMING2)..................... 4-24
4.5.3.4 Upper Panel Frame Buffer Base Address Register (UPBASE)........ 4-26
4.5.3.5 Lower Panel Frame Buffer Base Address Register (LPBASE) ........ 4-27
4.5.3.6 Interrupt Enable Register (INTREN)................................................. 4-28
4.5.3.7 CLCDC Control Register (CTRL) ..................................................... 4-29
4.5.3.8 Raw Interrupt Status Register (STATUS)......................................... 4-32
4.5.3.9 Masked Interrupt Status Register (INTERRUPT) ............................. 4-33
4.5.3.10 Interrupt Clear Register (INTCLR).................................................. 4-34
4.5.3.11 LCD Upper Panel and Lower Panel Frame Buffer Current
Address Register (UPCURR and LPCURR) ............................................ 4-35
4.5.3.12 256 × 16-bit Color Palette Register (PALETTE)............................. 4-36
4.5.4 ALI Register Reference ........................................................................... 4-38
4.5.5 ALI Memory Map ..................................................................................... 4-38
4.5.6 ALI Register Descriptions ........................................................................ 4-38
4.5.6.1 Setup Register (ALISETUP) ............................................................. 4-38
4.5.6.2 Control Register (ALICTRL) ............................................................. 4-39
4.5.6.3 Timing Delay Register 1 (ALITIMING1)............................................ 4-40
4.5.6.4 Timing Delay Register 2 (ALITIMING2)............................................ 4-41
4.6.1 STN Horizontal Timing ............................................................................ 4-42
4.6.2 STN Vertical Timing ................................................................................ 4-42
4.6.3 TFT Horizontal Timing ............................................................................. 4-42
4.6.4 TFT Vertical Timing ................................................................................. 4-42
4.6.5 AD-TFT/HR-TFT Horizontal Timing Waveforms...................................... 4-42
4.6.6 AD-TFT/HR-TFT Vertical Timing Waveforms.......................................... 4-42
5.1.1 Use for SSP and UART ............................................................................. 5-3
5.1.2 Changing Mode from Memory to Peripheral ............................................. 5-3
5.1.3 Interrupt, Error, and Status Registers........................................................ 5-4
5.1.3.1 Interrupts ............................................................................................ 5-4
5.1.4 External DMA Handshake Signal Timing .................................................. 5-4
5.2.1 Memory Map ............................................................................................. 5-5
5.2.2 Register Definitions ................................................................................... 5-6
5.2.2.1 Source Base Registers (SOURCELO and SOURCEHI) .................... 5-6
5.2.2.2 Destination Base Registers (DESTLO and DESTHI) ......................... 5-7
5.2.2.3 Maximum Count Register (MAX)........................................................ 5-8
5.2.2.4 Control Register (CTRL)..................................................................... 5-9
5.2.2.5 Current Source Registers (CURSHI and CURSLO)......................... 5-12
5.2.2.6 Current Destination Registers (CURDHI and CURDLO).................. 5-13
5.2.2.7 Terminal Count Register (TCNT)...................................................... 5-14
5.2.2.8 Interrupt Mask Register (MASK)....................................................... 5-15
5.2.2.9 Interrupt Clear Register (CLR).......................................................... 5-16
5.2.2.10 Status Register (STATUS) ............................................................. 5-17
Version 1.0
LH79524/LH79252 User's Guide