Table 11-72. Muxctl25 Register; Multiplexing Control 25 Register (Muxctl25) - Sharp LH79524 User Manual

I/O Configuration

11.2.2.36 Multiplexing Control 25 Register (MUXCTL25)

The MUXCTL25 Register allows software to configure a number of LH79524/LH79525 pins.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
11-54

Table 11-72. MUXCTL25 Register

31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
AN6 AN7
0 0 0 0
RW RW RW RW RW
Table 11-73. MUXCTL25 Fields
BIT NAME
31:16 /// Reserved Writing to these BIT has no effect. Reading returns 0.
AN6/PJ7/INT7 Assignment
00 = AN6
15:14 AN6
01 = PJ7
10 = INT7
11 = Reserved
AN7/PJ6/INT6 Assignment
00 = AN7
13:12 AN7
01 = PJ6
10 = INT6
11 = Reserved
AN5/PJ5/INT5 Assignment
00 = AN5
11:10 AN5
01 = PJ5
10 = INT5
11 = Reserved
AN8/PJ4 Assignment
00 = AN8
9:8 AN8
01 = PJ4
10 = Reserved
11 = Reserved
AN2/LL/Y+/PJ3 Assignment
00 = AN2/LL/Y+
7:6 AN2
01 = PJ3
10 = Reserved
11 = Reserved
27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
AN5 AN8
0 0 0 0 0
RW RW RW RW
0xFFFE5000 + 0xC0
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19
0 0 0 0
RO RO RO RO
6 5 4 3
AN2 AN9 AN4
0 0 0 0
RW RW RW RW
18 17 16
0 0 0
RO RO RO
2 1 0
AN3
0 0 0
RW RW RW