Table 14-11. Cpsr Register; Table 14-12. Cpsr Fields; Clock Prescale Register (Cpsr) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

14.2.2.5 Clock Prescale Register (CPSR)

The CPSR Register specifies the division factor by which the input HCLK is internally
divided before use. The value programmed into this register is a value from 2 to 254. This
register defaults to zero, but is double buffered and reads back 1s after Reset.
it resets to zero, it must be programmed prior to enabling the SSP.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:16
15:8
7:0

Table 14-11. CPSR Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
WO WO WO WO WO
/// Reserved Reading returns 0. Write the reset value.
/// Reserved Write as zero. Unpredictable behavior when read.
Clock Prescale Divisor
(SSPCLK), the SSP uses two divisors on the generated 5.6448 MHz Clock
Input (when using the recommended 11.2896 MHz crystal):
• This programmable prescaler in the Clock Prescaler register Divisor field
• A programmable clock rate divisor in the CTRL0 register (CTRL0:CPD)
DVSR
Program this field to the desired even-number eight-bit value between 2 and 254 for
DVSR shown in the equation (note that bit zero is always 0, hence DVSR is always
an even number).
SSPCLK is calculated as follows:
SSPCLK = ƒCLOCK INPUT/(DVSR × (1 + CPD))
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
WO WO WO RW
0xFFFC6000 + 0x010

Table 14-12. CPSR Fields

DESCRIPTION
To generate the bit rate and Serial Clock output
Version 1.0
Synchronous Serial Port
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
DVSR
0 0 0 0 0
RW RW RW RW RW
Because
17 16
0 0
RO RO
1 0
0 0
RW RO
14-15