Figure 5-1. Basic Dma Timing; Interrupt, Error, And Status Registers - Sharp LH79524 User Manual

Direct Memory Access Controller

5.1.3 Interrupt, Error, and Status Registers

The DMA Controller provides Interrupt, Error, and Status Registers for controlling the gen-
eration of an interrupt, error-handling control, and active-stream monitoring. Each stream
has its own interrupt flag, which is set after the last transfer completes. Each of the four
interrupt flags can be masked and cleared independently.
Each stream also has its own error flag. An error flag is set when the data stream transfer
is aborted due to an Error response from an AHB slave. Each of the four error flags can
be separately masked and cleared. The masked interrupt and error flags are all combined
into a single interrupt output.
5.1.3.1 Interrupts
The interrupt flags generated by the DMA Controller are combined and supplied to the
Interrupt Controller as a combined interrupt. See the Vectored Interrupt Controller chapter
for more information on interrupts.
5.1.4 External DMA Handshake Signal Timing
The basic signal timing for external DMA is illustrated in Figure 5-1. Additional timing is
available in the Data Sheet.
• DREQ Timing: Once asserted, DREQ must not transition from LOW to HIGH again until
after nDACK has been asserted.
• nDACK/DEOT Timing: Figure 5-1 indicates when nDACK and DEOT occur in relation to
an external bus access to/from the external peripheral that requested the DMA transfer.
This diagram shows the timing with relation to a single read or the last word of a burst
read from the requesting peripheral.
nDACK will be extended by wait states (either programmed or forced via the nWAIT pin) in
the same manner that the memory cycle is extended.
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
5-4
DREQ MAY
TRANSITON
DREQ
MUST NOT
TRANSITON
DREQ0,
DREQ1
DACK0
nDACK1

Figure 5-1. Basic DMA Timing

Version 1.0
LH79524/LH79525 User's Guide
tDREQ0L,
tDREQ1L
LH79525-5