Table 11-48. Muxctl19 Register; Table 11-49. Muxctl19 Fields; Multiplexing Control 19 Register (Muxctl19) - Sharp LH79524 User Manual

I/O Configuration

11.2.2.24 Multiplexing Control 19 Register (MUXCTL19)

The MUXCTL19 Register allows software to configure a number of LH79524/LH79525
pins. Bits marked 'LH79524 Only' read as 0 with all writes 'reserved' on the LH79525.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RESET
32-Bit
RW
ADDR
11-34

Table 11-48. MUXCTL19 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
PE7 PE6
0 0 0 0 0
0 0 0 0 0
RW RW RW RW RW

Table 11-49. MUXCTL19 Fields

BIT NAME
31:16 /// Reserved Reading returns 0. Write the reset value.
PE7/nWAIT/nDEOT Assignment
00 = PE7
15:14 PE7
01- = nWAIT
10 = nDEOT
11 = Reserved
PE6/LCDVEEN/LCDMOD Assignment
00 = PE6
13:12 PE6
01 = LCDVEEN
10 = LCDMOD
11 = Reserved
PL7/D31 Assignment (LH79524 Only)
00 = PL7
11:10 PL7
01 = D31
10 = Reserved
11 = Reserved
PE5/LCDVDDEN Assignment
00 = PE5
9:8 PE5
01 = LCDVDDEN
10 = Reserved
11 = Reserved
PL6/D30 Assignment (LH79524 Only)
00 = PL6
7:6 PL6
01 = D30
10 = Reserved
11 = Reserved
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
PL7 PE5 PL6/D30
0 0 0 0
1 0 0 0
RW RW RW RW
0xFFFE5000 + 0x90
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
PE4 PE3
0 0 0 0 0
1 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
PL5
0 0
0 1
RW RW