Table 1-4. Default Bus Master Priority; Ahb Bus Master Priority And Arbitration - Sharp LH79524 User Manual

Overview

1.5 AHB Bus Master Priority and Arbitration

The LH79524/LH79525 have five AHB masters - the ARM
Controller, the Color LCD Controller, USB Device, and the Ethernet Controller. Two of the
masters — the ARM
cating with all the memory controllers and peripherals. The LCD Controller, USB Device,
and Ethernet Controller interface to the main AHB bus via a slave interface for program-
ming and via a master interface for accessing SDRAM and Static Memory Controllers.
The default priorities for the five different AHB masters are indicated in Table 1-4.
1.6 Memory Interface Architecture
The LH79524/LH79525 provides the following data-path-management resources on chip:
• AHB and APB data buses
• 16KB of internal SRAM accessible by the ARM
Ethernet Controller, or LCD Controller
• A static and dynamic memory controller with a 24-bit address and 16/32-bit data
interface
• A 4-channel general purpose DMA controller
All system resources accessible by the LH79524/LH79525 are memory mapped. These
include external resources (e.g. ROM, PROM, SRAM, SDRAM, External Peripherals) and
internal resources (system configuration registers, peripheral configuration registers, and
internal memory).
The external memory space is partitioned into eight banks. Each bank spans 512MB. The
start address of each bank is fixed and is determined by the three highest order bits of the
32-bit AHB address. These banks define the type of resource being addressed. One bank
can only contain external static memory devices connected to the External Bus Interface
(EBI). Another bank can only contain external SDRAM devices connected to the EBI.
Another bank contains only the internal SRAM, connected to the AHB. Finally, another
bank is reserved for accessing the system configuration registers themselves, as well as
many of the peripheral control registers. See Table 1-5.
1-12
processor and the DMA controller — are capable of communi-
720T

Table 1-4. Default Bus Master Priority

PRIORITY BUS MASTER PRIORITY
1 (Highest) CLCD Controller
2 Ethernet
3 USB Device
4 DMA Controller
5 (Lowest) ARM720T Core (Default)
Version 1.0
LH79524/LH79525 User's Guide
processor, the DMA
720T
processor, DMA Controller,
720T