Table 7-60. Swaitpagex Register; Table 7-61. Swaitpagex Fields - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
7.5.2.25 Static Memory Page Mode Read Delay Registers (SWAITPAGEx)
The Static Memory Page Mode Read Delay Registers enable programming the delay for
Asynchronous Page Mode sequential accesses.
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:5
4:0

Table 7-60. SWAITPAGEx Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 7-61. SWAITPAGEx Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Asynchronous Page Mode Delay Number of Wait States for Asynchro-
nous Page Mode Read accesses after the first Read:
WAITPAGE
Asynchronous Page Mode Delay = (WAITPAGE + 1) HCLK cycles
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF1000 + 0x210 for SWAITPAGE0
0xFFFF1000 + 0x230 for SWAITPAGE1
0xFFFF1000 + 0x250 for SWAITPAGE2
0xFFFF1000 + 0x270 for SWAITPAGE3
FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
WAITPAGE
0 0 1 1 1
RO RO RW RW RW
17 16
0 0
RO RO
1 0
1 1
RW RW
7-57