Figure 4-10. Ad-Tft, Hr-Tft Horizontal Timing Diagram; Figure 4-11. Ad-Tft, Hr-Tft Vertical Timing Diagram - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
*
NOTE:
SYNCHRONIZATION)
SYNCHRONIZATION
(LCD VIDEO DATA)
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
*
CLCDCLK
(INTERNAL)
APBPERIPHCLKCTRL1:LCD AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED
CLKPRESCALE:LCDPS
(SHOWN FOR REFERENCE)
TIMING0:HSW
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2:BCD
TIMING2:IPC
TIMING2:CPL
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
16 × (TIMING0:PPL+1)
LCDEN
(INTERNAL DATA ENABLE)
LCDDCLK
(DELAYED FOR
AD-TFT, HR-TFT)
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
(DELAYED FOR
AD-TFT, HR-TFT)
LCDSPL
(AD-TFT, HR-TFT
START PULSE LEFT)
ALITIMING1:LPDEL
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
ALITIMING1:PSCLS
LCDCLS
LCDPS
LCDREV
Source is RCPC.

Figure 4-10. AD-TFT, HR-TFT Horizontal Timing Diagram

TIMING1:VSW
LCDSPS
(VERTICAL
1.5 µs - 4 µs
LCDLP
(HORIZONTAL
PULSE)
LCDVD[11:0]

Figure 4-11. AD-TFT, HR-TFT Vertical Timing Diagram

Color Liquid Crystal Display Controller
1 AD-TFT or HR-TFT HORIZONTAL LINE
001 002 003 004 005 006 007 008
PIXEL DATA
TIMING0:HSW +
TIMING0: HBP
001 002 003 004 005 006
1 LCDDCLK
ALITIMING2:SPLDEL
1 LCDDCLK
ALITIMING2:PS2CLS2
Version 1.0
320
317 318 319 320
LH79525-42
LH79525-43
4-47