Table 11-56. Muxctl21 Register; Table 11-57. Muxctl21 Fields; Multiplexing Control 21 Register (Muxctl21) - Sharp LH79524 User Manual

I/O Configuration

11.2.2.28 Multiplexing Control 21 Register (MUXCTL21)

The MUXCTL21 Register allows software to configure a number of LH79524/LH79525
pins. Bits marked 'LH79524 Only' read as 0 with all writes 'reserved' on the LH79525.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
11-42

Table 11-56. MUXCTL21 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RW

Table 11-57. MUXCTL21 Fields

BIT NAME
31:12 /// Reserved Reading returns 0. Write the reset value.
PF5/LCDVD11 Assignment
00 = PF5
11:10 PF5
01 = LCDVD11
10 = Reserved
11 = Reserved
PL3/LCDVD13 Assignment (LH79524 Only)
00 = PL3
9:8 PL3
01 = LCDVD13
10 = Reserved
11 = Reserved
PF4/LCDVD10 Assignment
00 = PF4
7:6 PF4
01 = LCDVD10
10 = Reserved
11 = Reserved
PL2/LCDVD12 Assignment (LH79524 Only)
00 = PL2
5:4 PL2
01 = LCDVD12
10 = Reserved
11 = Reserved
PF3/LCDVD9 Assignment
00 = PF3
3:2 PF3
01 = LCDVD9
10 = Reserved
11 = Reserved
PF2/LCDVD8 Assignment
00 = PF2
1:0 PF2
01 = LCDVD8
10 = Reserved
11 = Reserved
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
PF5 PL3 PF4
0 0 0 0
RW RW RW RW
0xFFFE5000 + 0xA0
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
PL2 PF3
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
PF2
0 0
RW RW