Figure 6-1. Emac Block Diagram; Theory Of Operation - Sharp LH79524 User Manual

Ethernet MAC Controller

6.1 Theory of Operation

This chapter assumes working knowledge of Ethernet protocol and the IEEE 802.3 spec-
ification. The full specification can be obtained at: http://standards.ieee.org/getieee802/
A simplified block diagram of the EMAC appears in Figure 6-1. It is handy to reference the
block diagram as the different interfaces are described in the succeeding sections. The EMAC
is identical for both the LH79524 and LH79525, and all descriptions in this chapter apply to
both devices. Following the Theory of Operation section is a programming example.
ADVANCED
PERPHERAL
BUS (APB)
ADVANCED HIGH
PERFORMANCE
BUS (AHB)
6-2
REGISTER
INTERFACE
CLOCK
GENERATION
HCLK
and
SYNCHRONIZATION
DMA
INTERFACE
TX
FIFO

Figure 6-1. EMAC Block Diagram

Version 1.0
INTERNAL TO
THE LH79524/LH79525
REGISTERS
CONTROL
REGISTERS
ADDRESS
CHECKING
ETHERNET
RECEIVE
RX
FIFO
ETHERNET
TRANSMIT
LH79524/LH79525 User's Guide
EXTERNAL TO
THE LH79524/LH79525
STATUS
ETHERMDIO
and
STATUS
ETHERMDC
BLOCK
ETHERRX[3:0]
ETHERRXER
BLOCK
ETHERRXDV
ETHERRXCLK
ETHERRTX[3:0]
ETHERTXER
ETHERCOL
ETHERCRS
BLOCK
ETHERTXEN
ETHERTXCLK
MII
LH79525-66