Sharp LH79524 User Manual page 229

External Memory Controller
In the Figure, nCSx is asserted coincident (with a small propagation delay) with the address
becoming valid (Valid Address in the Figure). Data becomes valid another small propaga-
tion delay later. Unlike Read transactions, nWE (or nBLEx) assertion is always delayed one
HCLK cycle, time 'A0' in the Figure. The nBLEx signal has the same timing as nWE for write
to 8-bit devices that use the byte lane enables instead of the write enables.
The nWE (or nBLEx) signal remains asserted for one HCLK cycle, denoted 'B0' in
Figure 7-12. At the end of 'B0', the nWE (or nBLEx) signal is deasserted and the data is
latched into the external memory device. Valid address is held for one additional cycle
before deassertion, as is the Chip Select.
Wait states behave slightly differently for Write transactions than for Reads. Instead
of the length of the Write cycle (tWC) being the sum of the value programmed into the
SWAITWENx and SWAITWRx registers, it has the following relationship:
tWC = tA0 + tB0 + tB1 ... tBn + C, where the length of each term is one HCLK period, and
'n' is the value programmed in the respective register.
The minimum value for the equation is tWC = tA0 +tB0 + C, and is therefore the zero wait
state timing.
Note that additional 'A' terms (delaying the assertion of nWE or nBLEx) do not add wait
states. This also requires that: SWAITWRx
Figure 7-13 shows the results of programming the SWAITWRx and SWAITWENx regis-
ters. In Timing A, SWAITWENx ('A') = 0x0, and SWAITWRx ('B') = 0x2. As always, nCSx
precedes nWE (nBLEx) by one HCLK period (A0). Then, instead of the nWE (nBLEx) sig-
nal deasserting one HCLK period later at the end of B0, it is delayed two wait states, B1
and B2, and the signal deasserts on the rising edge at the end of B2.
7-14
≥
SWAITWENx.
Version 1.0
LH79524/LH79525 User's Guide