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Overview
1.3.1 Bus Clocking Modes
The ARM720T core (including the cache) and its AHB interface can be operated using
either the Fastbus operation mode or one of two Standard clocking modes (Synchronous
or Asynchronous).
The clocking modes can have significant impact on power consumption and system
throughput, depending upon the application and the speed of external memory. The
ARM720T core and the AHB are clocked by separate signals and the core is capable of
operation at a much higher frequency than the AHB. This higher core speed benefits appli-
cations running from cache more than applications requiring frequent AHB access
because each AHB access requires the core and AHB be re-synchronized. Parallel core
and AHB operations can continue with buffered writes to the AHB, but all Read accesses
will stall the core until the bus access is completed. Programmers can use the three bus
clocking modes to maximize throughput by reducing the re-synchronization delays (the
number of wait states).
1.3.1.1 Standard Bus Clocking Modes
The Standard bus clocking modes are useful for designs involving low-cost, low-speed
memory, where operation of the core at a faster speed than the AHB is desired. These
modes involve:
• A programmable choice of Synchronous or Asynchronous operation
• Two clocks: HCLK and FCLK.
The AHB interface is controlled by the bus clock (HCLK), qualified by an nWAIT signal.
Figure 1-2 shows the Standard mode clocking arrangement. The core and cache are
driven by FCLK while HCLK drives the bus. FCLK must always be greater than or equal
to HCLK, on a cycle-by-cycle basis. The nWAIT signal can extend a memory access by
inserting entire HCLK cycles into the bus cycle timing.
NOTE: This is a conceptual drawing
1-6
ARM720T
FCLK
HCLK
WAIT SIGNAL
Figure 1-2. Standard Clocking Modes
Version 1.0
LH79524/LH79525 User's Guide
CORE
CACHE
AHB
INTERFACE
ADVANCED
HIGH-PERFORMANCE
BUS (AHB)
LH79525-49
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