Sharp LH79524 User Manual page 14

Table of Contents
Chapter 15 - Timers
15.1 Theory of Operation ..................................................................................... 15-2
15.2 Register Reference ...................................................................................... 15-6
Chapter 16 - UARTs
16.1 Theory of Operation ..................................................................................... 16-2
16.2 Interrupts ...................................................................................................... 16-7
16.3 Register Reference ...................................................................................... 16-7
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15.1.1 Counter Clear Upon Compare Match .................................................... 15-3
15.1.2 Capture Signal Sampling....................................................................... 15-4
15.1.3 PWM Mode............................................................................................ 15-4
15.1.3.1 Timer Interrupts .............................................................................. 15-5
15.2.1 Memory Map ......................................................................................... 15-6
15.2.2 Register Descriptions ............................................................................ 15-7
15.2.2.1 Timer 0 Control Register (CTRL0).................................................. 15-7
15.2.2.2 Timer 0 Compare/Capture Control Register (CMP_CAP_CTRL0) 15-8
15.2.2.3 Timer 0 Interrupt Control Register (INTEN0)................................ 15-10
15.2.2.4 Timer 0 Status Register (STATUS0) ............................................ 15-11
15.2.2.5 Timer 0 Counter Register (CNT0) ................................................ 15-12
15.2.2.6 Timer 0 Compare Registers (T0CMPn)........................................ 15-13
15.2.2.7 Timer 0 Capture Registers (CAPn)............................................... 15-14
15.2.2.8 Timer 1 Control Register (CTRL1)................................................ 15-15
15.2.2.9 Timer 1 Interrupt Control Register (INTEN1)................................ 15-17
15.2.2.10 Timer 1 Status Register (STATUS1) .......................................... 15-18
15.2.2.11 Timer 1 Counter Register (CNT1) .............................................. 15-19
15.2.2.12 Timer 1 Compare Registers (T1CMPn)...................................... 15-20
15.2.2.13 Timer 1 Capture Registers (T1CAPn) ........................................ 15-21
15.2.2.14 Timer 2 Control Register (CTRL2).............................................. 15-22
15.2.2.15 Timer 2 Interrupt Control Register (INTEN2).............................. 15-24
15.2.2.16 Timer 2 Status Register (STATUS2) .......................................... 15-25
15.2.2.17 Timer 2 Counter Register (CNT2) .............................................. 15-26
15.2.2.18 Timer 2 Compare Registers (T2CMPn)...................................... 15-27
15.2.2.19 Timer 2 Capture Registers (T2CAPn) ........................................ 15-28
16.1.1 Transmitting Data .................................................................................. 16-3
16.1.2 Receive Data Frame ............................................................................. 16-3
16.1.3 Nine-bit Mode ........................................................................................ 16-4
16.1.4 Status Conditions .................................................................................. 16-4
16.1.5 On-Chip DMA Capabilities .................................................................... 16-5
16.1.6 Programming the SIR ............................................................................ 16-5
16.1.7 Hardware Flow Control.......................................................................... 16-6
16.1.7.1 RTS Flow Control ........................................................................... 16-6
16.1.7.2 CTS Flow Control ........................................................................... 16-6
16.1.8 Programming Control Registers ............................................................ 16-6
16.2.1 UARTINTR ............................................................................................ 16-7
16.3.1 Memory Map ......................................................................................... 16-7
16.3.2 Register Definitions ............................................................................... 16-8
16.3.2.1 Data Register (UARTDR) ............................................................... 16-8
16.3.2.2 Receive Status/Error Clear Register (UARTRSR/UARTECR) ....... 16-9
Version 1.0
LH79524/LH79252 User's Guide