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LH79524/LH79525 User's Guide
17.1.5 DMA Operation
DMA access to the Endpoint FIFOs requires both the DMA controller and the endpoint to be
programmed for the selected DMA Mode. Details are given in the following sections. (It will
be helpful to refer to the register descriptions in Section 17.2 before reading these sections.)
17.1.5.1 DMA Mode 0: OUT Endpoints
For operation in DMA Mode 0, these steps describe programming an OUT endpoint:
1.
Program the proper interrupt enable bit in the OUT Interrupt Enable (OIE) register to
1 to enable that interrupt.
2.
Program the INDEX register to the EP number.
3.
Then program the OUTCSR2:USB_DMA_EN bit to 0. This disables DMA bulk trans-
fers for Mode 0 operation.
4.
When a packet has been received by the USB Device, it sends an interrupt to the VIC.
Software should then program the DMA registers with:
– ADDRx: Memory address to store packet
– COUNTx: Size of packet (determined by reading the OUTCOUNTx register)
– CNTLx: 0x0009 (see Section 17.2.3.14 for the CNTLx register description)
The DMA Controller then requests bus mastership and transfers the packet to memory.
When it completes the transfer, an interrupt is asserted to the VIC.
5.
Software must then program the OUTCSR1:OUT_PKT_RDY bit to 0, indicating that
there is no packet waiting for transfer.
17.1.5.2 DMA Mode 0: IN Endpoints
For operation in DMA Mode 0, these steps describe programming an IN endpoint:
1.
Program the proper interrupt enable bit in the IN Interrupt Enable (IIE) register to 1 to
enable that interrupt.
2.
Program the INDEX register to the EP number.
3.
Program INCSR2:USB_DMA_EN bit to 0 to disable DMA bulk transfers for Mode 0.
4.
When the FIFO becomes available in the USB Device, an interrupt is sent to the VIC.
Software should then program the DMA registers with:
– ADDRx: Memory address of packet to send
– COUNTx: Size of packet to be sent
– CNTLx: 0x000B
The DMA controller then requests bus mastership and transfers the packet to the Endpoint
FIFO. When it completes the transfer, an interrupt is asserted to the VIC.
5.
Software must program the INCSR1:IN_PKT_RDY bit to 0, indicating that the FIFO is
available for packet data.
Version 1.0
Universal Serial Bus Device
17-5
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