On-Chip Dma Capabilities - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

16.1.5 On-Chip DMA Capabilities

UART0 can be programmed to utilize the on-chip DMA to reduce processor bandwidth
required to service UART activities. DMA functions support burst transfers on the receive
channel, transmission channel, or both. When using DMA, the transfer size must be set
to 8 bits.
• When DMA is enabled on the receive channel, a DMA request is issued when the
receive FIFO reaches its programmed high water mark. Once the DMA block services
the request, a new one is issued when the FIFO fills above its high water mark.
• When DMA is enabled on the transmit channel, a request is issued when the transmit
channel FIFO falls below its low water mark. The request is reissued if the FIFO remains
below that level when the DMA request has been serviced, or the next time that the FIFO
falls below that level.
NOTE: After reaching the watermark value and generating and interrrupt when transferring Receive data to
DMA requests are masked when the UART issues an error interrupt. If the UART is in the
Character Mode, only the DMA Single Transfer Mode (transferring one character per DMA
operation) can operate, since only one character can be transferred to or from the FIFOs at
any time. As a result, the programmed watermark level is not relevant in Character Mode.
DMA requests and setup are handled by programming the DMA Controller. This is
described in Chapter 5 of this User's Guide.
NOTE: Care must be used in selecting receive Watermark values when using DMA transfers. The Watermark
16.1.6 Programming the SIR
Serial Infrared (SIR) functions are supported to speeds of 115.2 kbps, half-duplex. The
Encoder/Decoder (SIR ENDEC) also supports normal 3/16 bit-durations and low-power
bit-durations. For low-power mode bit-durations, the reference clock which is input to the
UART can be divided by values from 1 to 512 (decimal), for use as the SIR baud clock.
The SIR system is a half-duplex system; the SIR cannot receive while it is transmitting.
The IrDA SIR physical layer specifies a minimum 10 μs delay between transmission and
reception. This delay must be implemented by software.
memory using DMA, data remains in the Receive FIFO; there will be one entry less than the setting
of the watermark. For example, if the watermark is set at 8, seven data entries remain in the Receive
FIFO after DMA completes. These elements must be transferred using programmed copying rather
than DMA.
must be no less than the number of bytes in a DMA Burst. Setting the Watermark to a lesser value
than the DMA Burst size results in storing erraneous data.
Version 1.0
UARTs
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